The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Mar. 25, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Yong Lu, Hefei, CN;

Minghung Hsieh, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76805 (2013.01); H01L 21/31111 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 28/91 (2013.01); H01L 2221/1063 (2013.01);
Abstract

Embodiments of the present application provide a semiconductor structure and its manufacturing method. The method for manufacturing a semiconductor structure includes: providing a substrate and a dielectric layer located on the substrate, the substrate being provided therein with a conductive structure; etching a certain thickness of the dielectric layer to form a first groove; performing an isotropic etching process on the dielectric layer located at the bottom of the first groove to form a second groove, a maximum width of the second groove being greater than a bottom width of the first groove in a direction parallel with a surface of the substrate; and etching the dielectric layer located at the bottom of the second groove to form a third groove exposing the conductive structure.


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