The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Todd R. Coons, Hillsboro, OR (US);

Michael Rutigliano, Hillsboro, OR (US);

Joe F. Walczyk, Tigard, OR (US);

Abram M. Detofsky, Tigard, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); G02B 6/12 (2006.01); G02B 6/30 (2006.01); G02B 6/34 (2006.01); H01L 25/075 (2006.01); H01L 33/58 (2010.01); H01L 33/62 (2010.01); H01L 23/367 (2006.01); H04B 10/40 (2013.01);
U.S. Cl.
CPC ...
G02B 6/4201 (2013.01); G02B 6/34 (2013.01); H01L 25/0756 (2013.01); H01L 33/62 (2013.01); G02B 6/12019 (2013.01); G02B 6/30 (2013.01); H01L 23/367 (2013.01); H01L 33/58 (2013.01); H04B 10/40 (2013.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.


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