The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2024
Filed:
Jun. 20, 2022
Nanjing University of Posts and Telecommunications, Jiangsu, CN;
Nantong Institute of Nanjing University of Posts and Telecommunications Co., Ltd., Jiangsu, CN;
Zhikuang Cai, Jiangsu, CN;
Yunbo Wang, Jiangsu, CN;
Jian Song, Jiangsu, CN;
Guopeng Zhou, Jiangsu, CN;
Jiafei Yao, Jiangsu, CN;
Binbin Xu, Jiangsu, CN;
Henglu Wang, Jiangsu, CN;
Zixuan Wang, Jiangsu, CN;
Yufeng Guo, Jiangsu, CN;
Abstract
Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.