The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

May. 23, 2022
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Teng-Hao Yeh, Hsinchu County, TW;

Hang-Ting Lue, Hsinchu, TW;

Shang-Chi Yang, Changhua County, TW;

Fu-Nian Liang, New Taipei, TW;

Ken-Hui Chen, Taipei, TW;

Chun-Hsiung Hung, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 5/06 (2006.01); G11C 11/4072 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 5/063 (2013.01); G11C 11/4072 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01);
Abstract

A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.


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