The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Apr. 04, 2023
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

David Edward Bien, Glendale, AZ (US);

Xu Jason Ma, Chandler, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/018 (2006.01); H03K 17/10 (2006.01); H03K 17/687 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018528 (2013.01); H03K 17/102 (2013.01); H03K 17/6872 (2013.01);
Abstract

A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.


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