The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Dec. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ming-Fa Chen, Taichung, TW;

Sung-Feng Yeh, Taipei, TW;

Tzuan-Horng Liu, Taoyuan, TW;

Chao-Wen Shih, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/563 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/481 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.


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