The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Dec. 27, 2021
Applicant:

Yibu Semiconductor Co., Ltd., Shanghai, CN;

Inventor:

Weiping Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49833 (2013.01); H01L 21/486 (2013.01); H01L 23/5381 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/49816 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/80 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11912 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01);
Abstract

The present disclosure provides a method for forming a semiconductor package and the semiconductor package. The method comprises attaching an interconnect device to a semiconductor substrate, and flip-chip mounting at least two chips over the interconnect device and the semiconductor substrate. Each chip includes at least one first bump of a first height and at least one second bump of a second height formed on a front surface hereof, the second height being greater than the first height. The method further comprises bonding the at least one second conductive bump of each of the at least two chips to the upper surface of the semiconductor substrate and bonding the first conductive bump of each of the at least two chips to the upper surface of the interconnect device Thus, the method uses a relatively simple and low cost packaging process to achieve high-density interconnection wiring in a package.


Find Patent Forward Citations

Loading…