The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2024
Filed:
Mar. 15, 2022
Kioxia Corporation, Tokyo, JP;
Wataru Moriyama, Yokohama, JP;
Hayato Konno, Yokohama, JP;
Takao Nakajima, Yamato, JP;
Fumihiro Kono, Yokohama, JP;
Masaki Fujiu, Yokohama, JP;
Kiyoaki Iwasa, Yokohama, JP;
Tadashi Someya, Edogawa, JP;
KIOXIA CORPORATION, Tokyo, JP;
Abstract
A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.