The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2024
Filed:
Feb. 08, 2020
Intel Ndtm Us Llc, Santa Clara, CA (US);
Deepak Thimmegowda, Fremont, CA (US);
Brian J. Cleereman, Boise, ID (US);
Srivardhan Gowda, Boise, ID (US);
Jui-Yen Lin, Hillsboro, OR (US);
Liu Liu, Dalian, CN;
Krishna Parat, Palo Alto, CA (US);
Jong Sun Sel, Dalian, CN;
Baosuo Zhou, Redwood, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.