The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Apr. 06, 2022
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Robert Paul Haase, San Pedro, CA (US);

Jyotshna Bhandari, Villach, AT;

Heimo Hofer, Bodensdorf, AT;

Ling Ma, Redondo Beach, CA (US);

Ashita Mirchandani, Torrance, CA (US);

Harsh Naik, El Segundo, CA (US);

Martin Poelzl, Ossiach, AT;

Martin Henning Vielemeyer, Villach, AT;

Britta Wutte, Feistritz, AT;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/4236 (2013.01); H01L 29/456 (2013.01); H01L 29/66734 (2013.01);
Abstract

A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.


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