The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Jan. 06, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Cheng Chou, Tainan County, TW;

Shiu-Ko Jangjian, Tainan, TW;

Cheng-Ta Wu, Chiayi County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/02164 (2013.01); H01L 21/02304 (2013.01); H01L 21/02312 (2013.01); H01L 21/3247 (2013.01); H01L 21/762 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01);
Abstract

A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.


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