The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Jul. 10, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chien-Li Kuo, Hsinchu, TW;

Chin-Fu Kao, Taipei, TW;

Chen-Shien Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4882 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 21/56 (2013.01); H01L 24/27 (2013.01); H01L 24/743 (2013.01); H01L 24/75 (2013.01); H01L 2224/214 (2013.01);
Abstract

A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.


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