The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Mar. 22, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Ferdinando Bedeschi, Biassono, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 16/04 (2006.01); H10B 43/20 (2023.01);
U.S. Cl.
CPC ...
G11C 13/0026 (2013.01); G11C 13/0004 (2013.01); G11C 16/0483 (2013.01); H10B 43/20 (2023.02); G11C 2213/71 (2013.01);
Abstract

Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.


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