The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jul. 29, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chao-I Wu, Hsinchu County, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/84 (2023.02); H10B 63/30 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/881 (2023.02);
Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes word lines, channel layer, gate dielectric layers, a conductive pillar and a storage pillar. The word lines extend along a first direction over a substrate, and are vertically spaced apart from one another. The channel layers respectively line along a sidewall of one of the word lines. The gate dielectric layers respectively line between one of the word lines and one of the channel layers. The conductive pillar and the storage pillar penetrate through the channel layers. The storage pillar includes an inner electrode, a switching layer and an outer electrode. The switching layer wraps around the inner electrode. The outer electrode laterally surrounds the switching layer, and includes annulus portions vertically spaced apart from one another and each in lateral contact with a corresponding one of the channel layers.


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