The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jul. 29, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Scott J. Derner, Boise, ID (US);

Charles L. Ingalls, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/00 (2023.02); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); H01L 29/78 (2013.01); H01L 29/7827 (2013.01); H10B 12/50 (2023.02);
Abstract

Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.


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