The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jul. 07, 2021
Applicant:

Semiconductor Components Industries, Llc, Scottsdale, AZ (US);

Inventors:

Subhash Srinivas Pidaparthi, Santa Clara, CA (US);

Andrew P. Edwards, Santa Clara, CA (US);

Clifford Drowley, Santa Clara, CA (US);

Kedar Patel, Santa Clara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0615 (2013.01); H01L 21/26546 (2013.01); H01L 21/266 (2013.01); H01L 21/3245 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.


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