The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jul. 01, 2022
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Harold Pilo, Underhill, VT (US);

Shishir Kumar, Uttar Pradesh, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/30 (2006.01); G11C 29/40 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
G11C 29/40 (2013.01); G11C 29/30 (2013.01); G11C 2029/3202 (2013.01);
Abstract

A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.


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