The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2024
Filed:
Feb. 26, 2020
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Assignee:
SYNOPSYS, INC., Mountain View, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/337 (2020.01); G06F 111/08 (2020.01); G06F 119/22 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/337 (2020.01); G06F 2111/08 (2020.01); G06F 2119/22 (2020.01);
Abstract
Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.
Le, Jiayong. (2024). Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation (U.S. Patent No. 12112108). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12112108
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile