The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Dec. 06, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Theron Lee Lewis, Rochester, MN (US);

David J. Braun, St. Charles, MN (US);

James D. Bielick, Pine Island, MN (US);

John R. Dangler, Rochester, MN (US);

Timothy P. Younger, Rochester, MN (US);

Timothy Jennings, Rochester, MN (US);

Jennifer I. Bennett, Rochester, MN (US);

Stephen Michael Hugo, Stewartville, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 13/516 (2006.01); H01R 12/57 (2011.01); H01R 43/02 (2006.01);
U.S. Cl.
CPC ...
H01R 13/516 (2013.01); H01R 43/0256 (2013.01); F16B 2200/77 (2023.08); H01R 12/57 (2013.01);
Abstract

A first apparatus includes an electrical connector with an outer shell and an inner wafer, where the inner wafer is configured to slide into a cavity of the outer shell. The first apparatus further includes a shape-memory alloy coupled to a void in the outer shell and configured to interfere with an area on the inner wafer. A second apparatus includes an OTS connector with an outer shell and an inner wafer, where the inner wafer is configured to slide into a cavity of the outer shell. The second apparatus further includes a plurality of SMT leads of the inner wafer configured to mount onto a plurality of landing pads on a PCBA. The second apparatus includes a shape-memory alloy coupled to a void in the outer shell and configured to interfere with the inner wafer preventing movement of the inner wafer within the outer shell of OTS connector.


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