The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Jan. 17, 2022
Applicant:

Dialog Semiconductor (Uk) Limited, London, GB;

Inventors:

Ernesto Gutierrez, III, Swindon, GB;

Jesus Mennen Belonio, Jr., Neubiberg, DE;

Shou Cheng Eric Hu, Taichung, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/64 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/647 (2013.01); H01L 21/56 (2013.01); H01L 21/76877 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/5389 (2013.01); H01L 23/642 (2013.01); H01L 24/14 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/18 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19015 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.


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