The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Jan. 24, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Mengmeng Wang, Hefei, CN;

Hsin-Pin Huang, Hefei, CN;

Qiang Zhang, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/764 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01);
Abstract

The disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure. The method for manufacturing the semiconductor structure comprises: a substrate, in which a first protective structure is formed, is provided; a first dielectric layer is formed on the substrate; and a second protective structure is formed in the first dielectric layer and the substrate. A projection of the second protective structure and a projection of the first protective structure in a direction perpendicular to a surface of the substrate are at least partially overlapped, and there is a spacing between a projection of the second protective structure and a projection of the first protective structure in a direction along the surface of the substrate.


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