The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Aug. 24, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yoshinori Fujiwara, Boise, ID (US);

Takuya Tamano, Boise, ID (US);

Jason M. Johnson, Nampa, ID (US);

Kevin G. Werhane, Kuna, ID (US);

Daniel S. Miller, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/02 (2006.01); G11C 29/00 (2006.01); G11C 29/24 (2006.01); G11C 29/44 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 29/789 (2013.01); G11C 29/027 (2013.01); G11C 29/24 (2013.01); G11C 29/4401 (2013.01); G11C 29/46 (2013.01);
Abstract

An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.


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