The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Oct. 15, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Armin Saeedi Vahdat, Burlington, MA (US);

John Hautala, Beverly, MA (US);

Johannes M. van Meer, Middleton, MA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/20 (2023.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H10B 41/23 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/20 (2023.01); H10B 43/23 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/20 (2023.02); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01);
Abstract

A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.


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