The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Sep. 20, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Guan-Yao Tu, Hsinchu, TW;

Su-Jen Sung, Hsinchu County, TW;

Tze-Liang Lee, Hsinchu, TW;

Hong-Wei Chan, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/477 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0665 (2013.01); H01L 21/477 (2013.01); H01L 23/5283 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01);
Abstract

A method includes forming a transistor over a front side of a substrate; forming a front-side interconnect structure over the transistor, the front-side interconnect structure comprising layers of conductive lines, and conductive vias interconnecting the layers of conductive lines; forming a first bonding layer over the front-side interconnect structure; forming a second bonding layer over a carrier substrate; bonding the front-side interconnect structure to the carrier substrate by pressing the first bonding layer against the second bonding layer; and forming a backside interconnect structure over a backside of the substrate after bonding the front-side interconnect structure to the carrier substrate.


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