The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Dec. 15, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Thomas Anthony Empante, San Jose, CA (US);

Avgerinos V. Gelatos, Scotts Valley, CA (US);

Zhibo Yuan, Santa Clara, CA (US);

Liqi Wu, San Jose, CA (US);

Joung Joo Lee, San Jose, CA (US);

Byunghoon Yoon, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 27/092 (2013.01); H01L 21/28518 (2013.01); H01L 21/76843 (2013.01);
Abstract

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.


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