The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Oct. 14, 2022
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Harold Pilo, Underhill, VT (US);

Shishir Kumar, Noida, IN;

Anurag Garg, Cupertino, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/2297 (2013.01); G11C 11/2255 (2013.01); G11C 11/2259 (2013.01);
Abstract

Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.


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