The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2024
Filed:
Feb. 25, 2021
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Inventors:
Yongqing Wang, Wuhan, CN;
Siping Hu, Wuhan, CN;
Assignee:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 23/00 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 24/06 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract
Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes providing a substrate, forming memory cells over the substrate, depositing a first dielectric layer to cover the memory cells, forming at least one contact pad over the substrate, depositing a second dielectric layer over the at least one contact pad, forming first connecting pads over the second dielectric layer, bonding the first connecting pads with second connecting pads of a peripheral structure, and exposing the at least one contact pad from a back side of the substrate.