The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Dec. 04, 2021
Applicant:

Yibu Semiconductor Co., Ltd., Shanghai, CN;

Inventor:

Weiping Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/4985 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/82 (2013.01); H01L 24/95 (2013.01); H01L 24/96 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81143 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/8212 (2013.01); H01L 2224/82203 (2013.01); H01L 2224/95001 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/15311 (2013.01);
Abstract

The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.


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