The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Mar. 19, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Purakh Raj Verma, Singapore, SG;

Kuo-Yuh Yang, Hsinchu County, TW;

Chia-Huei Lin, Hsinchu, TW;

Chu-Chun Chang, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 21/56 (2006.01); H01L 21/71 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/56 (2013.01); H01L 21/71 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 2223/6661 (2013.01); H01L 2224/05624 (2013.01);
Abstract

A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.


Find Patent Forward Citations

Loading…