The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Jul. 30, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Byeung Chul Kim, Boise, ID (US);

Davide Resnati, Vimercate, IT;

Gianpietro Carnevale, Bottanuco, IT;

Shyam Surthi, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02);
Abstract

Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.


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