The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Oct. 11, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Yonggang Yang, Wuhan, CN;

Xiaohong Zhou, Wuhan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31144 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01);
Abstract

Methods for forming a 3D memory device are provided. A method includes the following operations. A stack structure is formed in a staircase region and an array region. A dielectric material layer is formed over the array region and the staircase region. An etch mask layer is coated over the dielectric material layer. The etch mask layer, on a first surface away from the dielectric material layer, is planarized. The dielectric material layer and a remaining portion of the etch mask layer are etched to form a dielectric layer over the staircase region and the array region.


Find Patent Forward Citations

Yang, Yonggang. (2024). Methods for forming dielectric layer in forming semiconductor device (U.S. Patent No. 12080560). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12080560

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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