The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Aug. 22, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jianhui Li, Shanghai, CN;

Yong Wu, Shanghai, CN;

Yihua Jin, Shanghai, CN;

Xueliang Zhong, Shanghai, CN;

Xiao Lin, Shanghai, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 9/30 (2018.01); G06F 9/355 (2018.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 9/30174 (2013.01); G06F 9/355 (2013.01); G06F 9/45554 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45583 (2013.01);
Abstract

An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.


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