The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

May. 20, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Sanjeev Kumar Jain, Kanata, CA;

Atul Katoch, Kanata, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/145 (2013.01);
Abstract

Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.


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