The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Mar. 24, 2020
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Raymond Chau, San Ramon, CA (US);

Chung-Ho Huang, San Jose, CA (US);

Henry Chan, Morgan Hill, CA (US);

Vincent Wong, Fremont, CA (US);

Yu Ding, Los Altos, CA (US);

Ngoc-Diep Nguyen, Portland, OR (US);

Gerramine Manuguid, Lake Oswego, OR (US);

Assignee:

LAM RESEARCH CORPORATION, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/418 (2006.01); C23C 14/54 (2006.01); C23C 16/52 (2006.01); H01J 37/32 (2006.01);
U.S. Cl.
CPC ...
G05B 19/41865 (2013.01); C23C 14/54 (2013.01); C23C 16/52 (2013.01); G05B 19/41885 (2013.01); H01J 37/32926 (2013.01); G05B 2219/39001 (2013.01); G05B 2219/45031 (2013.01); G05B 2219/45212 (2013.01); H01J 2237/334 (2013.01);
Abstract

For etching tools, a neural network model is trained to predict optimum scheduling parameter values. The model is trained using data collected from preventive maintenance operations, recipe times, and wafer-less auto clean times as inputs. The model is used to capture underlying relationships between scheduling parameter values and various wafer processing scenarios to make predictions. Additionally, in tools used for multiple parallel material deposition processes, a nested neural network based model is trained using machine learning. The model is initially designed and trained offline using simulated data and then trained online using real tool data for predicting wafer routing path and scheduling. The model improves accuracy of scheduler pacing and achieves highest tool/fleet utilization, shortest wait times, and fastest throughput.


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