The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Sep. 21, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Kun Zhang, Wuhan, CN;

Yuancheng Yang, Wuhan, CN;

Wenxi Zhou, Wuhan, CN;

Wei Liu, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Liang Chen, Wuhan, CN;

Yanhong Wang, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/20 (2023.01); H01L 25/065 (2023.01); H10B 41/41 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/20 (2023.02); H01L 25/0652 (2013.01); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02);
Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first semiconductor layer, an array of NAND memory strings, and a first peripheral circuit of the array of NAND memory strings. Sources of the array of NAND memory strings are in contact with a first side of the first semiconductor layer. The first peripheral circuit includes a first transistor in contact with a second side of the first semiconductor layer opposite to the first side. The second semiconductor structure includes a second semiconductor layer and a second peripheral circuit of the array of NAND memory strings. The second peripheral circuit includes a second transistor in contact with the second semiconductor layer.


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