The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2024
Filed:
Mar. 17, 2020
Fujian Jinhua Integrated Circuit Co., Ltd., Fujian, CN;
Chung-Yen Chou, Fujian, CN;
Chih-Yuan Chen, Fujian, CN;
Qinfu Zhang, Fujian, CN;
Chao-Wei Lin, Fujian, CN;
Chia-Yi Chu, Fujian, CN;
Jen-Chieh Cheng, Fujian, CN;
Jen-Kuo Wu, Fujian, CN;
Huixian Lai, Fujian, CN;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;
Abstract
A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer () having an upper portion () and a lower portion (). The upper portion () is multi-layer structure having an increased thickness without changing a thickness of the lower portion (). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion () designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion. In this way, current leakage between word lines (WL) and the active areas (AA) can be mitigated.