The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Aug. 13, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

BingYu Zhu, Hefei, CN;

Hai-Han Hung, Hefei, CN;

Yin-Kuei Yu, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 28/82 (2013.01); H01L 27/0805 (2013.01); H01L 28/91 (2013.01); H10B 12/01 (2023.02); H10B 12/02 (2023.02); H10B 12/315 (2023.02);
Abstract

Provided are a semiconductor structure and a method for preparing the same. The method for preparing a semiconductor structure includes: a substrate is provided; a stacked structure is formed on the substrate; a first capacitor having a first bottom electrode, a first dielectric layer and a first top electrode is formed in the stacked structure, in which the first bottom electrode is of a columnar structure; and a second capacitor having a second bottom electrode, a second dielectric layer and a second top electrode is formed on the first capacitor, in which the second bottom electrode is of a concave structure. The second dielectric layer is formed between the second bottom electrode and the second top electrode, and the second dielectric layer is further formed between the second bottom electrodes of adjacent second capacitors.


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