The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2024
Filed:
Apr. 24, 2023
Sunrise Memory Corporation, San Jose, CA (US);
Khandker Nazrul Quader, Santa Clara, CA (US);
Robert Norman, Pendleton, OR (US);
Frank Sai-keung Lee, San Jose, CA (US);
Christopher J. Petti, Mountain View, CA (US);
Scott Brad Herner, Portland, OR (US);
Siu Lung Chan, San Jose, CA (US);
Sayeef Salahuddin, Walnut Creek, CA (US);
Mehrdad Mofidi, San Jose, CA (US);
Eli Harari, Saratoga, CA (US);
SUNRISE MEMORY CORPORATION, San Jose, CA (US);
Abstract
An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.