The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Apr. 25, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Feng-Wei Kuo, Hsinchu County, TW;

Hui-Yu Lee, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G01R 31/317 (2006.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); G01R 31/31704 (2013.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01); H01L 2224/051 (2013.01); H01L 2224/11011 (2013.01); H01L 2924/14 (2013.01);
Abstract

A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.


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