The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Jan. 12, 2022
Applicants:

Etron Technology, Inc., Hsinchu, TW;

Invention and Collaboration Laboratory Pte. Ltd., Singapore, SG;

Inventors:

Chao-Chun Lu, Taipei, TW;

Chun Shiah, Hsinchu, TW;

Bor-Doou Rong, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4074 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 11/406 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01);
Abstract

The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.


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