The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2024
Filed:
Jan. 06, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Johnny Chiahao Li, Hsinchu, TW;
Sheng-Hsiung Chen, Hsinchu, TW;
Tzu-Ying Lin, Hsinchu, TW;
Yung-Chen Chien, Kaohsiung, TW;
Jerry Chang Jui Kao, Taipei, TW;
Xiangdong Chen, San Diego, CA (US);
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.