The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Apr. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chieh Lee, Hsinchu, TW;

Chia-En Huang, Hsinchu, TW;

Yi-Ching Liu, Hsinchu, TW;

Wen-Chang Cheng, Hsinchu, TW;

Yih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 11/22 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); G11C 5/04 (2013.01); G11C 5/063 (2013.01); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); H10B 51/10 (2023.02); H10B 51/30 (2023.02); H10B 51/40 (2023.02); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01);
Abstract

In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed above the active semiconductor layer, and a memory module formed in the region. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.


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