The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Aug. 31, 2017
Applicants:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

The University of California, Los Angeles (Ucla), Los Angeles, CA (US);

Inventors:

Huan-Neng Chen, Taichung, TW;

Chewn-Pu Jou, Hsinchu, TW;

Feng Wei Kuo, Hsinchu, TW;

Lan-Chou Cho, Hsinchu, TW;

Wen-Shiang Liao, Miaoli, TW;

Yanghyo Kim, Los Angeles, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); G02B 6/10 (2006.01); G02B 6/42 (2006.01); G02B 6/43 (2006.01); G02F 1/01 (2006.01); G02F 1/025 (2006.01); H01L 23/552 (2006.01); H01P 3/08 (2006.01); H01P 3/16 (2006.01); H04B 10/40 (2013.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); G02B 6/102 (2013.01); G02B 6/4274 (2013.01); G02B 6/43 (2013.01); G02F 1/011 (2013.01); G02F 1/0121 (2013.01); G02F 1/025 (2013.01); H01L 23/552 (2013.01); H01P 3/081 (2013.01); H01P 3/16 (2013.01); H04B 10/40 (2013.01);
Abstract

Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.


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