The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Dec. 04, 2023
Applicant:

Eliyan Corporation, Santa Clara, CA (US);

Inventor:

Ramin Farjadrad, Los Altos, CA (US);

Assignee:

Eliyan Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); H01L 25/065 (2023.01); H01L 25/07 (2006.01); H01L 25/075 (2006.01); H01L 25/11 (2006.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 25/0652 (2013.01); H01L 25/072 (2013.01); H01L 25/0753 (2013.01); H01L 25/115 (2013.01);
Abstract

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chiplet disposed on the common substrate. The first IC chiplet includes at least one processing element. A communications fabric switchably couples to the at least one processing element. A peripheral gearbox chiplet (PGC) includes a first port having a second memory-agnostic interface coupled to the first memory-agnostic interface of the first IC chiplet. The PGC includes a second port having a memory interface of a first type and interface conversion circuitry disposed between the second memory-agnostic interface and the memory interface of the first type.


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