The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Sep. 11, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Qingqing Wang, Hubei, CN;

Wei Xu, Hubei, CN;

Wenbin Zhou, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/50 (2023.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02);
Abstract

A method for forming a 3D memory device is disclosed. The method includes forming an alternating dielectric stack on a substrate. Then a plurality of channel structures and dummy channel structures vertically penetrating the alternating dielectric stack are formed, The channel structures are located in a core region, and the dummy channel structures are located in a staircase region. A gate line silt structure is formed vertically penetrating the alternating dielectric stack and laterally extending in a first direction. The gate line silt structure includes a narrow portion that has a reduced width along a second direction different from the first direction.


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