Three-dimensional memory devices with drain select gate cut and methods for forming and operating the same

Abstract

Embodiments of 3D memory devices and methods for forming and operating the same are disclosed. In an example, a 3D memory device includes a memory stack, a plurality of memory strings, and a plurality of bit line contacts each in contact with a respective one of the plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each memory string extends vertically through the memory stack. The conductive layers include a plurality of drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The plurality of memory strings are divided into a plurality of regions that are a minimum repeating unit of the memory stack in a plan view. Each of the plurality of memory strings abuts at least one of the DSG lines.