The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2024

Filed:

May. 11, 2022
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Timothy Strauss, Granger, IN (US);

Jon Scott Choy, Austin, TX (US);

Michael A. Sadd, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/46 (2006.01); G11C 29/12 (2006.01); G11C 29/20 (2006.01); G11C 29/36 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G11C 29/1201 (2013.01); G11C 29/20 (2013.01); G11C 29/36 (2013.01); G11C 2029/3602 (2013.01);
Abstract

Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.


Find Patent Forward Citations

Loading…