The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2024

Filed:

Jul. 13, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Ferdinando Bedeschi, Biassono, IT;

Jeffrey E. Koelling, Fairview, TX (US);

Hari Giduturi, Folsom, CA (US);

Riccardo Muzzetto, Arcore, IT;

Corrado Villa, Sovico, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0026 (2013.01); G11C 13/0004 (2013.01); G11C 13/0028 (2013.01); G11C 13/003 (2013.01); G11C 13/0033 (2013.01);
Abstract

Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.


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