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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12048137 B1

PDFFull Text
Date of Patent:
Jul. 23, 2024

Filed:

Aug. 17, 2021

Semiconductor arrangement and method of manufacture

Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Po-Sheng Wang, Zhubei, TW;

Ru-Yu Wang, New Taipei, TW;

Yangsyu Lin, New Taipei, TW;

You-Cheng Xiao, Taiping, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu, TW;

Attorney:

Cooper Legal Group, LLC

Primary Examiner:

Anthony Ho

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H10B 10/18 (2023.02); H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 27/0922 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.

Find Patent Forward Citations

Wang, Po-Sheng. (2024). Semiconductor arrangement and method of manufacture (U.S. Patent No. 12048137). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12048137

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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