The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Jan. 26, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chao-Ching Cheng, Hsinchu, TW;

Hung-Li Chiang, Hsinchu, TW;

Chun-Chieh Lu, Hsinchu, TW;

Ming-Yang Li, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/04 (2006.01); H01L 29/20 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7606 (2013.01); H01L 29/04 (2013.01); H01L 29/2003 (2013.01); H01L 29/454 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional '2D' semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.


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